82801CA Datasheet, PDF (238/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LAN Controller Registers (B1:D8:F0)
7.1.6
7.1.7
7.1.8
7.1.9
SCC—Sub Class Code Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Ah
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Sub Class Code. 8-bit value that specifies the sub-class of the device as an Ethernet controller.
BCC—Base Class Code Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Bh
Default Value: 02h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Base Class Code. 8-bit value that specifies the base class of the device as a network controller.
CLS—Cache Line Size Register (LAN Controller—B1:D8:F0)
Offset Address: 0Ch
Default Value: 00h
Attribute:
Size:
RW
8 bits
Bit
Description
7:5 Reserved.
Cache Line Size (CLS)—RW.
00 = Memory Write and Invalidate (MWI) command will not be used by the integrated LAN Controller.
01 = MWI command will be used with Cache Line Size set to 8 DWords (only set if a value of 08h is
4:3
written to this register).
10 = MWI command will be used with Cache Line Size set to 16 DWords (only set if a value of 10h is
written to this register).
11 = Invalid. MWI command will not be used.
2:0 Reserved.
PMLT—PCI Master Latency Timer Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Dh
Default Value: 00h
Attribute:
Size:
RW
8 bits
Bit
Description
7:3
Master Latency Timer Count (MLTC)—RW. Defines the number of PCI clock cycles that the
integrated LAN Controller may own the bus while acting as bus master.
2:0 Reserved.
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Intel^® 82801CA ICH3-S Datasheet