82801CA Datasheet, PDF (204/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.17.2
Bus Arbitration
Several masters may attempt to get on the bus at the same time by driving the SMBDATA line low
to signal a start condition. The ICH3 must continuously monitor the SMBDATA line. When the
ICH3 is attempting to drive the bus to a 1 by letting go of the SMBDATA line, and it samples
SMBDATA low, then some other master is driving the bus and the ICH3 must stop transferring
data.
If the ICH3 sees that it has lost arbitration, the condition is called a collision. The ICH3 sets the
BUS_ERR bit in the Host Status Register, and if enabled, generates an interrupt or SMI#. The
processor is responsible for restarting the transaction.
When the ICH3 is a SMBus master, it drives the clock. When the ICH3 is sending address or
command as an SMBus master, or data bytes as a master on writes, it drives data relative to the
clock it is also driving. It does not start toggling the clock until the start or stop condition meets
proper setup and hold time. The ICH3 also guarantees minimum time between SMBus transactions
as a master.
The ICH3 supports the same arbitration protocol for both the SMBus and the System Management
(SMLINK) interfaces.
5.17.3 Bus Timing
5.17.3.1
5.17.3.2
Clock Stretching
Some devices may not be able to handle their clock toggling at the rate that the ICH3 as an SMBus
master would like. They have the capability of stretching the low time of the clock. When the ICH3
attempts to release the clock (allowing the clock to go high), the clock remains low for an extended
period of time.
The ICH3 must monitor the SMBus clock line after it releases the bus to determine whether to
enable the counter for the high time of the clock. While the bus is still low, the high time counter
must not be enabled. Similarly, the low period of the clock can be stretched by an SMBus master if
it is not ready to send or receive data.
Bus Time Out (Intel^® ICH3 as SMBus Master)
If there is an error in the transaction, such that an SMBus device does not signal an acknowledge,
or holds the clock lower than the allowed time-out time, the transaction will time out. The ICH3
will discard the cycle, and set the DEV_ERR bit. The time out minimum is 25 ms. The time-out
counter inside the ICH3 starts after the last bit of data is transferred by the ICH3 and it is waiting
for a response. The 25 ms is a count of 800 RTC clocks.
204
Intel^® 82801CA ICH3-S Datasheet