82801CA Datasheet, PDF (254/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LAN Controller Registers (B1:D8:F0)
7.2.10
7.2.11
Power Management Driver (PMDR) Register
Offset Address: 1Bh
Default Value: 00h
Attribute:
Size:
R/WC
8 bits
The ICH3’s internal LAN Controller provides an indication in the PMDR that a wake-up event has
occurred.
Bit
Description
Link Status Change Indication—R/WC.
7
0 = Software clears this bit by writing a 1 to the bit location.
1 = The link status change bit is set following a change in link status.
Magic Packet*—R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
6
1 = This bit is set when a Magic Packet is received regardless of the Magic Packet wake-up disable
bit in the configuration command and the PME Enable bit in the power management control/
status register.
Interesting Packet—R/WC.
5
0 = Software clears this bit by writing a 1 to the bit location.
1 = This bit is set when an “interesting” packet is received. Interesting packets are defined by the
LAN Controller packet filters.
4:1 Reserved.
PME Status—R/WC. This bit is a reflection of the PME status bit in the Power Management Control/
Status Register (PMCSR).
0
0 = Software clears this bit by writing a 1 to the bit location. This also clears the PME status bit in
the PMCSR and de-asserts the PME signal.
1 = Set upon a wake-up event, independent of the PME enable bit.
General Control Register
Offset Address: 1Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:4 Reserved. These bits should be set to 0000b.
LAN Connect Software Reset—R/W.
3
0 = Cleared by software to begin normal LAN Connect operating mode. Software must not attempt
to access the LAN Connect interface for at least 1 ms after clearing this bit.
1 = Software can set this bit to force a reset condition on the LAN Connect interface.
2 Reserved. This bit should be set to 0.
Deep Power-Down on Link Down Enable.
0 = Disable.
1
1 = The ICH3’s internal LAN Controller may enter a deep power-down state (sub-3 mA) in the D2
and D3 power states while the link is down. In this state, the LAN Controller does not keep link
integrity. This state is not supported for point-to-point connection of two end stations.
0 Reserved.
254
Intel^® 82801CA ICH3-S Datasheet