82801CA Datasheet, PDF (290/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.1.26
9.1.27
FDD/LPT_DEC—LPC I/F FDD & LPT Decode Ranges
Register (LPC I/F—D31:F0)
Offset Address: E1h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:5 Reserved.
FDD Decode Range—R/W. Determines which range to decode for the FDD Port
4 _{0 = 3F0h–3F5h, 3F7h (Primary)}
1 = 370h–2FFh (Secondary)
3:2 Reserved.
LPT Decode Range—R/W. This field determines which range to decode for the LPTPort.
00 = 378h–37Fh and 778h–77Fh
1:0 _{01 = 278h–27Fh (port 279h is read only) and 678h–67Fh}
10 = 3BCh–3BEh and 7BCh–7BEh
11 = Reserved
SND_DEC—LPC I/F Sound Decode Ranges Register
(LPC I/F—D31:F0)
Offset Address: E2h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:6 Reserved.
MSS Decode Range—R/W. This field determines which range to decode for the Microsoft Sound
System (MSS)
5:4 ^{00 = 530h–537h}
01 = 604h–60Bh
10 = E80h–E87h
11 = F40h–F47h
MIDI Decode Range—R/W. This bit determines which range to decode for the Midi Port
3 _{0 = 330h–331h}
1 = 300h–301h
2 Reserved.
SB16 Decode Range—R/W. This field determines which range to decode for the Sound Blaster 16
(SB16) Port
1:0 ^{00 = 220h–233h}
01 = 240h–253h
10 = 260h–273h
11 = 280h–293h
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Intel^® 82801CA ICH3-S Datasheet