82801CA Datasheet, PDF (141/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
The ICH3 supports the Pending Break Event (PBE) indication from the processor using the FERR#
signal. The following rules apply:
1. When STPCLK# is detected active by the processor, the FERR# signal from the processor is
redefined to indicate whether an interrupt is pending. The signal is active low (i.e., FERR# will
be low to indicate a pending interrupt).
2. When the ICH3 asserts STPCLK#, it latches the current state of the FERR# signal and
continues to present this state to the FERR# state machine (independent of what the FERR#
pin does after the latching).
3. When the ICH3 detects the Stop-Grant cycle, it starts looking at the FERR# signal as a break
event indication. If FERR# is sampled low, a break event is indicated. This forces a transition
to the C0 state.
4. When the processor detects the deassertion of STPCLK#, the processor starts driving the
FERR# signal with the natural value (i.e., the value it would do if the pin was not muxed). The
time from STPCLK# inactive to the FERR# signal transition back to the native function must
be less than 120 ns.
5. The ICH3 waits at least 180 ns after deasserting STPCLK# and then starts using the FERR#
signal for an indication of a floating point error. The maximum time that the ICH3 may wait is
bounded such that it must have a chance to look at the FERR# signal before reasserting
STPCLK#. Based on current implementation, that maximum time would be 240 ns (8 PCI
clocks).
The break event associated with this new mechanism does not need to set any particular status bit,
since the pending interrupt will be serviced by the processor after returning to the C0 state.
5.12.6.1
Throttling Using STPCLK#
Throttling is used to lower power consumption or reduce heat. The ICH3 asserts STPCLK# to
throttle the processor clock and the processor appears to temporarily enter a C2 state. After a
programmable time, the ICH3 deasserts STPCLK# and the processor appears to return to the C0
state. This allows the processor to operate at reduced average power, with a corresponding decrease
in performance. Two methods are included to start throttling:
1. Software enables a timer with a programmable duty cycle. The duty cycle is set by the
THTL_DTY field and the throttling is enabled using the THTL_EN field. This is known as
Manual Throttling. The period is fixed to be in the non-audible range, due to the nature of
switching power supplies.
2. A Thermal Override condition (THRM# signal active for >2 seconds) occurs that
unconditionally forces throttling, independent of the THTL_EN bit. The throttling due to
Thermal Override has a separate duty cycle (THRM_DTY) which may vary by field and
system. The Thermal Override condition will end when THRM# goes inactive.
Throttling due to the THRM# signal has higher priority than the software initiated throttling.
Throttling does not occur when the system is in a C2 state, even if Thermal override occurs.
Intel^® 82801CA ICH3-S Datasheet
141