SH7751 Datasheet, PDF (999/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
The error detection bits are set even when the interrupts are masked.
Bits 31 to 14—Reserved: These bits always return 0 when read. Always write 0 to these bits
when writing.
Bit 13—Master Broken Interrupt (MST_BRKN): Detects when the master granted with bus
privileges does not start a transaction (FRAME not asserted) within 16 clocks. For the SH7751,
see 22.12, Usage Notes.
Bit 12—Target Bus Timeout Interrupt (TGT_BUSTO): Neither TRDY nor STOP are not
returned within 16 clocks in the case of the first data transfer, or within 8 clocks in the case of
second and subsequent data transfers. For the SH7751, see 22.12, Usage Notes.
Bit 11—Master Bus Timeout Interrupt (MST_BUSTO): Indicates the detection that IRDY was
not asserted within 8 clock cycles in a transaction initiated by a device including PCIC.
Bits 10 to 4—Reserved: These bits always return 0 when read. Always write 0 to these bits when
writing.
Bit 3—Target Abort Interrupt (TGT_ABORT): Indicates the termination of transaction by
target abort when a device other than the PCIC is operating as the bus master.
Bit 2—Master Abort Interrupt (MST_ABORT): Indicates the termination of transaction by
master abort when a device other than the PCIC is operating as the bus master.
Bit 1—Write Data Parity Error Interrupt (DPERR_WT): Indicates the detection of the
assertion of PERR in a data write operation when a device other than the PCIC is operating as the
bus master.
Bit 0—Read Data Parity Error Interrupt (DPERR_RD): Indicates the detection of the
assertion of PERR in a data read operation when a device other than the PCIC is operating as the
bus master.
Rev.4.00 Oct. 10, 2008 Page 901 of 1122
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