SH7751 Datasheet, PDF (216/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Caches
Effective address
31
25
13 12 11 10
54 2 0
IIX
22
[12]
Entry
selection
Address array
8
(way 0, way 1)
0
Tag
V
[11:5]
Longword (LW)
selection
3
Data array (way 0, way 1)
LRU
LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
MMU
19
255 19 bits 1 bit
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 1 bit
Compare Compare
way-0 way-1
Read data
Hit signal
Figure 4.7 Configuration of Instruction Cache (SH7751R)
• Tag
Stores the upper 19 bits of the 29-bit external address of the data line to be cached. The tag is
not initialized by a power-on or manual reset.
• V bit (validity bit)
Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is
valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
Rev.4.00 Oct. 10, 2008 Page 118 of 1122
REJ09B0370-0400