SH7751 Datasheet, PDF (65/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13.2.13 Refresh Time Constant Register (RTCOR) ......................................................... 391
13.2.14 Refresh Count Register (RFCR) .......................................................................... 392
13.2.15 Notes on Accessing Refresh Control Registers.................................................... 392
13.3 Operation........................................................................................................................... 393
13.3.1 Endian/Access Size and Data Alignment............................................................. 393
13.3.2 Areas .................................................................................................................... 400
13.3.3 SRAM Interface ................................................................................................... 405
13.3.4 DRAM Interface .................................................................................................. 413
13.3.5 Synchronous DRAM Interface............................................................................. 427
13.3.6 Burst ROM Interface............................................................................................ 457
13.3.7 PCMCIA Interface ............................................................................................... 460
13.3.8 MPX Interface...................................................................................................... 471
13.3.9 Byte Control SRAM Interface ............................................................................. 485
13.3.10 Waits between Access Cycles.............................................................................. 489
13.3.11 Bus Arbitration..................................................................................................... 490
13.3.12 Master Mode ........................................................................................................ 493
13.3.13 Slave Mode .......................................................................................................... 494
13.3.14 Cooperation between Master and Slave ............................................................... 495
13.3.15 Notes on Usage .................................................................................................... 495
Section 14 Direct Memory Access Controller (DMAC).......................................... 497
14.1 Overview........................................................................................................................... 497
14.1.1 Features................................................................................................................ 497
14.1.2 Block Diagram (SH7751) .................................................................................... 500
14.1.3 Pin Configuration (SH7751) ................................................................................ 501
14.1.4 Register Configuration (SH7751) ........................................................................ 502
14.2 Register Descriptions ........................................................................................................ 504
14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) .......................................... 504
14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3).................................. 505
14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)......................... 506
14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)................................... 507
14.2.5 DMA Operation Register (DMAOR)................................................................... 515
14.3 Operation........................................................................................................................... 517
14.3.1 DMA Transfer Procedure..................................................................................... 517
14.3.2 DMA Transfer Requests ...................................................................................... 520
14.3.3 Channel Priorities................................................................................................. 523
14.3.4 Types of DMA Transfer....................................................................................... 526
14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing .......................... 535
14.3.6 Ending DMA Transfer ......................................................................................... 549
14.4 Examples of Use ............................................................................................................... 552
Rev.4.00 Oct. 10, 2008 Page lxv of xcviii
REJ09B0370-0400