SH7751 Datasheet, PDF (841/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Smart Card Interface
nth transfer frame
Retransferred frame
Transfer frame n+1
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp ₅
Ds D0 D1 D2 D3 D4
RDRF
2
4
PER
1
3
Figure 17.11 Retransfer Operation in SCI Receive Mode
Retransfer Operation when SCI is in Transmit Mode: Figure 17.12 illustrates the retransfer
operation when the SCI is in transmit mode.
1. If an error signal is sent back from the receiving side after transmission of one frame is
completed, the FER/ERS bit in SCSSR1 is set to 1. If the RIE bit in SCSCR1 is enabled at this
time, an ERI interrupt request is generated. The FER/ERS bit in SCSSR1 should be cleared to
0 before the next parity bit is sampled.
2. The TEND bit in SCSSR1 is not set for a frame for which an error signal indicating an error is
received.
3. If an error signal is not sent back from the receiving side, the FER/ERS bit in SCSSR1 is not
set.
4. If an error signal is not sent back from the receiving side, transmission of one frame, including
a retransfer, is judged to have been completed, and the TEND bit in SCSSR1 is set to 1. If the
TIE bit in SCSCR1 is enabled at this time, a TXI interrupt request is generated.
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Retransferred frame
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
TDRE
Transfer from SCTDR1
to SCTSR1
TEND
FER/ERS
Transfer from SCTDR1
to SCTSR1
2
4
1
3
Transfer frame n+1
Ds D0 D1 D2 D3 D4
Transfer from SCTDR1
to SCTSR1
Figure 17.12 Retransfer Operation in SCI Transmit Mode
Rev.4.00 Oct. 10, 2008 Page 743 of 1122
REJ09B0370-0400