SH7751 Datasheet, PDF (515/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
Burst Access: In addition to the normal DRAM access mode in which a row address is output in
each data access, a fast page mode is also provided for the case where consecutive accesses are
made to the same row. This mode allows fast access to data by outputting the row address only
once, then changing only the column address for each subsequent access. Normal access or burst
access using fast page mode can be selected by means of the burst enable (BE) bit in MCR. The
timing for burst access using fast page mode is shown in figure 13.16.
If the access size exceeds the set bus width, burst access is performed. In a 32-byte transfer, the
first access comprises a longword that includes the data requiring access. The remaining accesses
are performed on 32-byte boundary data that includes the relevant data. In burst transfer,
wraparound writing is performed for 32-byte data.
CKIO
Address
Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tpc
Row
c1
c2
c8
CSn
RD/WR
RAS
CASn
D31–D0
(read)
D31–D0
(write)
d1
d2
d1
d2
d8
d8
BS
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.16 DRAM Burst Access Timing
Rev.4.00 Oct. 10, 2008 Page 417 of 1122
REJ09B0370-0400