SH7751 Datasheet, PDF (87/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Figure 23.35 DRAM Bus Cycles (1) RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001 (2)
RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 010 ......................................... 1037
Figure 23.36 DRAM Bus Cycle (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000,
TRC [2:0] = 001)................................................................................................ 1038
Figure 23.37 DRAM Bus Cycle (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000,
TPC [2:0] = 001) ................................................................................................ 1039
Figure 23.38 DRAM Burst Bus Cycle (EDO Mode, RCD [1:0] = 01, AnW [2:0] = 001,
TPC [2:0] = 001) ................................................................................................ 1040
Figure 23.39 DRAM Burst Bus Cycle (EDO Mode, RCD [1:0] = 01, AnW [2:0] = 001,
TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width) ........................................ 1041
Figure 23.40 DRAM Burst Bus Cycle: RAS Down Mode State
(EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000) .............................................. 1042
Figure 23.41 DRAM Burst Bus Cycle: RAS Down Mode Continuation
(EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000) .............................................. 1043
Figure 23.42 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 00,
AnW [2:0] = 000, TPC [2:0] = 001)................................................................... 1044
Figure 23.43 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 01,
AnW [2:0] = 001, TPC [2:0] = 001)................................................................... 1045
Figure 23.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 01, AnW [2:0] = 001,
TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width) ........................................ 1046
Figure 23.45 DRAM Burst Bus Cycle: RAS Down Mode State (Fast Page Mode,
RCD [1:0] = 00, AnW [2:0] = 000).................................................................... 1047
Figure 23.46 DRAM Burst Bus Cycle: RAS Down Mode Continuation
(Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000) ....................................... 1048
Figure 23.47 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
(TRAS [2:0] = 000, TRC [2:0] = 001) ............................................................... 1049
Figure 23.48 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
(TRAS [2:0] = 001, TRC [2:0] = 001) ............................................................... 1050
Figure 23.49 DRAM Bus Cycle: DRAM Self-Refresh (TRC [2:0] = 001) ............................. 1051
Figure 23.50 PCMCIA Memory Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000,
No Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One
External Wait...................................................................................................... 1052
Figure 23.51 PCMCIA I/O Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000,
No Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait +
One External Wait .............................................................................................. 1053
Figure 23.52 PCMCIA I/O Bus Cycle (TED [2:0] = 001, TEH [2:0] = 001,
One Internal Wait, Bus Sizing) .......................................................................... 1054
Figure 23.53 MPX Basic Bus Cycle: Read (1) 1st Data (One Internal Wait) (2) 1st Data
(One Internal Wait + One External Wait) .......................................................... 1055
Rev.4.00 Oct. 10, 2008 Page lxxxvii of xcviii
REJ09B0370-0400