SH7751 Datasheet, PDF (610/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
Bits 11 to 8—Resource Select 3 to 0 (RS3–RS0): These bits specify the transfer request source.
Bit 11: Bit 10: Bit 9: Bit 8:
RS3 RS2 RS1 RS0 Description
0
0
0
0
External request, dual address mode*¹*³ (external address
space → external address space)
(Initial value)
1
Setting prohibited
1
0
External request, single address mode
External address space → external device*^1,*³
1
External request, single address mode
External device → external address space*^1,*³
1
0
0
Auto-request (external address space → external address
space)*²
1
Auto-request (external address space → on-chip peripheral
module)*²
1
0
Auto-request (on-chip peripheral module → external address
space)*²
1
Setting prohibited
1
0
0
0
SCI transmit-data-empty interrupt transfer request
(external address space → SCTDR1)*²
1
SCI receive-data-full interrupt transfer request
(SCRDR1 → external address space)*²
1
0
SCIF transmit-data-empty interrupt transfer request
(external address space → SCFTDR2)*²
1
SCIF receive-data-full interrupt transfer request
(SCFRDR2 → external address space)*²
1
0
0
TMU channel 2 (input capture interrupt, external address space
→ external address space)*²
1
TMU channel 2 (input capture interrupt)
(external address space → on-chip peripheral module)*²
1
0
TMU channel 2 (input capture interrupt)
(on-chip peripheral module → external address space)*²
1
Setting prohibited
Notes: 1. External request specifications are valid only for channels 0 and 1. Requests are not
accepted for channels 2 and 3 in normal DMA mode.
2. Dual address mode
3. In DDT mode, an external request specification is possible for channels 0, 1, 2, and 3.
Rev.4.00 Oct. 10, 2008 Page 512 of 1122
REJ09B0370-0400