SH7751 Datasheet, PDF (424/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. Timer Unit (TMU)
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2–TPSC0): In channels 0 to 2, these bits select the
TCNT count clock.
When the on-chip RTC output clock is selected as the count clock for a channel, that channel can
operate even in module standby mode. When another clock is selected, the channel does not
operate in standby mode.
Bit 2: TPSC2
0
1
Bit 1: TPSC1
0
1
0
1
Bit 0: TPSC0
0
1
0
1
0
1
0
1
Description
Counts on Pck/4
(Initial value)
Counts on Pck/16
Counts on Pck/64
Counts on Pck/256
Counts on Pck/1024
Reserved (Do not set)
Counts on on-chip RTC output clock (Do not
set in channels 3 and 4)
Counts on external clock (Do not set in
channels 3 and 4)
12.2.7 Input Capture Register 2 (TCPR2)
TCPR2 is a 32-bit read-only register for use with the input capture function, provided only in
channel 2.
The input capture function is controlled by means of the input capture control bits (ICPE1, ICPE0)
and clock edge bits (CKEG1, CKEG0) in TCR2. When input capture occurs, the TCNT2 value is
copied into TCPR2. The value is set in TCPR2 only when the ICPF bit in TCR2 is 0.
TCPR2 is not initialized by a power-on or manual reset, or in standby mode.
Bit: 31
30
29
2
1
0
·············
Initial value:
Undefined
R/W: R
R
R
R
R
R
Rev.4.00 Oct. 10, 2008 Page 326 of 1122
REJ09B0370-0400