SH7751 Datasheet, PDF (554/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
• Burst Write
Figure 13.40 is the timing chart for a burst-write operation with a burst length of 8. In this LSI,
a burst write takes place when a copy-back of the cache or a 32-byte transfer of data by the
DMAC takes place. In a burst-write operation, a WRITA command that include auto
precharging, is issued during the Tc1 cycle that follows the Tr cycle in which the ACTV
command is output. During the write cycle, the data to be written is output along with the write
command. With a write command that includes an auto precharge, precharging is of the
relevant bank of the synchronous DRAM and takes place on completion of the write
command, so no new command that accesses the same bank can be issued until precharging
has been completed. For this reason, the Trwl cycles are added as a period of waiting for
precharging to start after the write command has been issued. This is additional to the
precharge-waiting cycle as used in read access. The Trwl cycles delay the issuing of new
commands to the same bank. The setting of the TRWL2 to TRWL0 bits of MCR selects the
number of Trwl cycles. The data between 32-byte boundaries are written in a wraparound way.
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
Tr Trw Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Trw1 Trw1 Tpc
Row
Row
H/L
Row
c1
D31–D0
(write)
BS
CKE
DACKn
(SA: IO → memory)
c1
c2
c3
c4
c5
c6
c7
c8
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.40 Basic Timing of a Burst Write to Synchronous DRAM
Rev.4.00 Oct. 10, 2008 Page 456 of 1122
REJ09B0370-0400