SH7751 Datasheet, PDF (212/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Caches
4.3.10 Notes on Using OC RAM Mode (SH7751R Only) when in Cache Enhanced Mode
When in cache enhanced mode (CCR.EMODE = 1) on the SH7751R, and the OC RAM mode, in
which half of the operand cache is used as internal RAM, is selected (CCR.ORA = 1), data in
RAM may be updated incorrectly.
Conditions Under which Problem Occurs: Incorrect data may be written to RAM when the
following four conditions are satisfied.
Condition 1: Cache enhanced mode (CCR.EMODE = 1) is specified.
Condition 2: The RAM mode (CCR.ORA = 1) in which half of the operand cache is used as RAM
is specified.
Condition 3: An exception or an interrupt occurs.
Note: This includes a break triggered by a debugging tool swapping an instruction (a break
occurring when a TRAPA instruction or undefined instruction code H'FFFD is swapped
for an instruction).
Condition 4: A store instruction (MOV, FMOV, AND.B, OR.B, XOR.B, MOVCA.L, STC.L, or
STS.L) that accesses internal RAM (H'7C000000 to H'7FFFFFFF) exists within four
words after the instruction associated with the exception or interrupt described in
condition 3. This includes cases where the store instruction that accesses internal
RAM itself generates an exception.
Description: When the problem occurs, 8 bytes of incorrect data is written to the 8-byte boundary
that includes an address that differs by H'2000 from the address accessed by the store instruction
that accesses internal RAM mentioned in condition 4. For example, when a long word is stored at
address H'7C000204, the 8 bytes of data in the internal RAM mapped to addresses H'7C002200 to
H'7C002207 becomes corrupted.
Rev.4.00 Oct. 10, 2008 Page 114 of 1122
REJ09B0370-0400