SH7751 Datasheet, PDF (33/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
14.7.4 DMA Channel 591
Control Registers 0-
7(CHCR0-CHCR7)
Bit 17-Acknowledge
Mode (AM)
14.8.3 Transfer
596
Channel Notification in
DDT Mode
Table 14.17 Function
of BAVL
15.1 Overview
603
15.3.3 Multiprocessor 644
Communication
Function
Revision (See Manual for Details)
Description amended
In normal DMA mode, this bit is valid only in CHCR0 and
CHCR1. In DDT mode, it is valid in CHCR0–CHCR7. (DDT
mode: TDACK)
Description amended
When the DMAC is set up for eight-channel external request
acceptance in DDT mode (DMAOR.DBL = 1), the ID [1:0] bits
and the simultaneous (on the timing of TDACK assertion)
assertion of ID2 from the BAVL (data bus available) pin are
used to notify the external device of the DMAC channel that is
to be used (see table 14.16, Notification of Transfer Channel in
Eight-Channel DDT Mode).
Table amended
TDACK = High
TDACK = Low
Function of BAVL
Bus available
Notification of channel number (ID2)
Description amended
The SCI supports a smart card interface. This is a serial
communication function supporting a subset of the ISO/IEC
7816-3 (identification cards) standard. For details, see section
17, Smart Card Interface.
Description amended
The transmitting station first sends the ID of the receiving
station with which it wants to perform serial communication as
data with the multiprocessor bit set to 1. It then sends transmit
data as data with the multiprocessor bit cleared to 0.
Rev.4.00 Oct. 10, 2008 Page xxxiii of xcviii
REJ09B0370-0400