SH7751 Datasheet, PDF (215/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Figure 4.6 shows the configuration of the instruction cache in the SH7751.
Figure 4.7 shows the configuration of the instruction cache in the SH7751R.
4. Caches
Effective address
31
26 25
13 12 11 10 9
543 21 0
IIX
22
MMU
19
[12]
8
0
Address array
Tag
V
[11:5]
Longword (LW) selection
3
Data array
LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
255 19 bits 1 bit
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits
Compare
Read data
Hit signal
Figure 4.6 Configuration of Instruction Cache (SH7751)
Rev.4.00 Oct. 10, 2008 Page 117 of 1122
REJ09B0370-0400