SH7751 Datasheet, PDF (959/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Bit 8—SERR Output Control (SER): Controls the SERR output.
Bit 8: SER
0
1
Description
SERR output disabled (Hi-Z)
SERR output enabled
22. PCI Controller (PCIC)
(Initial value)
Bit 7—Wait Cycle Control (WCC): Controls the address/data stepping. When WCC=1, address
and data are output in master write operations, only address is output in master read operations,
and only data is output in target read operations, at least in two clocks.
Bit 7: WCC
0
1
Description
Disable address/data stepping control
Enable address/data stepping control
(Initial value)
Bit 6—Parity Error Response (PER): Controls the device response when a parity error is
detected or a parity error report is received. PERR is asserted only when PER = 1.
Bit 6: PER
0
1
Description
Ignore detected parity errors
Respond to detected parity error
(Initial value)
Bit 5—VGA Pallet Snoop Control (VPS)
Bit 5: VPS
0
1
Description
VGA-compatible device
(Initial value)
The device does not respond to pallet register writes (not supported)
Bit 4—Memory Write and Invalidate Control (MWIE): Controls the issuance of memory and
invalidate command when the PCIC is operating as the master.
Bit 4: MWIE
0
1
Description
The device uses memory write
(Initial value)
The device can execute memory write and invalidate commands (not
supported)
Rev.4.00 Oct. 10, 2008 Page 861 of 1122
REJ09B0370-0400