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SH7751 Datasheet, PDF (557/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer | |||
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13. Bus State Controller (BSC)
CKIO
A25âA5
A4âA0
CSn
RD/WR
RD
D31âD0
(read)
BS
T1 Tw Twe TB2 TB1 Tw TB2 TB1 Tw TB2 TB1 Tw T2
RDY
DACKn
(SA: IO â memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.42 Burst ROM Wait Access Timing
Rev.4.00 Oct. 10, 2008 Page 459 of 1122
REJ09B0370-0400
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