SH7751 Datasheet, PDF (76/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Figure 4.4 Configuration of Write-Back Buffer ...................................................................... 111
Figure 4.5 Configuration of Write-Through Buffer................................................................. 111
Figure 4.6 Configuration of Instruction Cache (SH7751) ....................................................... 117
Figure 4.7 Configuration of Instruction Cache (SH7751R)..................................................... 118
Figure 4.8 Memory-Mapped IC Address Array ...................................................................... 121
Figure 4.9 Memory-Mapped IC Data Array ............................................................................ 122
Figure 4.10 Memory-Mapped OC Address Array..................................................................... 124
Figure 4.11 Memory-Mapped OC Data Array .......................................................................... 125
Figure 4.12 Memory-Mapped IC Address Array ...................................................................... 127
Figure 4.13 Memory-Mapped IC Data Array ............................................................................ 128
Figure 4.14 Memory-Mapped OC Address Array..................................................................... 130
Figure 4.15 Memory-Mapped OC Data Array .......................................................................... 131
Figure 4.16 Store Queue Configuration..................................................................................... 132
Section 5 Exceptions
Figure 5.1 Register Bit Configurations.................................................................................... 138
Figure 5.2 Instruction Execution and Exception Handling...................................................... 143
Figure 5.3 Example of General Exception Acceptance Order................................................. 145
Section 6 Floating-Point Unit
Figure 6.1 Format of Single-Precision Floating-Point Number............................................... 173
Figure 6.2 Format of Double-Precision Floating-Point Number ............................................. 174
Figure 6.3 Single-Precision NaN Bit Pattern........................................................................... 176
Figure 6.4 Floating-Point Registers......................................................................................... 178
Section 8 Pipelining
Figure 8.1 Basic Pipelines ....................................................................................................... 212
Figure 8.2 Instruction Execution Patterns................................................................................ 213
Figure 8.3 Examples of Pipelined Execution........................................................................... 225
Section 9 Power-Down Modes
Figure 9.1 STATUS Output in Power-On Reset ..................................................................... 255
Figure 9.2 STATUS Output in Manual Reset.......................................................................... 255
Figure 9.3 STATUS Output in Standby → Interrupt Sequence............................................... 256
Figure 9.4 STATUS Output in Standby → Power-On Reset Sequence .................................. 256
Figure 9.5 STATUS Output in Standby → Manual Reset Sequence ...................................... 257
Figure 9.6 STATUS Output in Sleep → Interrupt Sequence................................................... 257
Figure 9.7 STATUS Output in Sleep → Power-On Reset Sequence ...................................... 258
Figure 9.8 STATUS Output in Sleep → Manual Reset Sequence........................................... 259
Figure 9.9 STATUS Output in Deep Sleep → Interrupt Sequence ......................................... 260
Rev.4.00 Oct. 10, 2008 Page lxxvi of xcviii
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