SH7751 Datasheet, PDF (77/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Figure 9.10 STATUS Output in Deep Sleep → Power-On Reset Sequence ............................. 260
Figure 9.11 STATUS Output in Deep Sleep → Manual Reset Sequence ................................. 261
Figure 9.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation) .......... 262
Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation) ............. 263
Figure 9.14 Timing When Power Other than VDD-RTC Is Off................................................ 263
Figure 9.15 Timing When VDD-RTC Power Is Off → On....................................................... 264
Section 10 Clock Oscillation Circuits
Figure 10.1 (1) Block Diagram of CPG (SH7751)...................................................................... 269
Figure 10.1 (2) Block Diagram of CPG (SH7751R) ................................................................... 270
Figure 10.2 Block Diagram of WDT ......................................................................................... 280
Figure 10.3 Writing to WTCNT and WTCSR........................................................................... 284
Figure 10.4 Points for Attention when Using Crystal Resonator............................................... 287
Figure 10.5 Points for Attention when Using PLL Oscillator Circuit ....................................... 288
Section 11 Realtime Clock (RTC)
Figure 11.1 Block Diagram of RTC .......................................................................................... 292
Figure 11.2 Examples of Time Setting Procedures.................................................................... 309
Figure 11.3 Examples of Time Reading Procedures.................................................................. 311
Figure 11.4 Example of Use of Alarm Function........................................................................ 312
Figure 11.5 Example of Crystal Oscillation Circuit Connection ............................................... 314
Section 12 Timer Unit (TMU)
Figure 12.1 Block Diagram of TMU ......................................................................................... 316
Figure 12.2 Example of Count Operation Setting Procedure .................................................... 328
Figure 12.3 TCNT Auto-Reload Operation ............................................................................... 329
Figure 12.4 Count Timing when Operating on Internal Clock .................................................. 329
Figure 12.5 Count Timing when Operating on External Clock ................................................. 330
Figure 12.6 Count Timing when Operating on On-Chip RTC Output Clock............................ 330
Figure 12.7 Operation Timing when Using Input Capture Function ......................................... 331
Section 13 Bus State Controller (BSC)
Figure 13.1 Block Diagram of BSC........................................................................................... 337
Figure 13.2 Correspondence between Virtual Address Space and External Memory Space..... 341
Figure 13.3 External Memory Space Allocation ....................................................................... 343
Figure 13.4 Example of RDY Sampling Timing at which BCR4 Is Set
(Two Wait Cycles Are Inserted by WCR2)............................................................ 362
Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR................................................. 393
Figure 13.6 Basic Timing of SRAM Interface........................................................................... 406
Figure 13.7 Example of 32-Bit Data Width SRAM Connection ............................................... 407
Rev.4.00 Oct. 10, 2008 Page lxxvii of xcviii
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