SH7751 Datasheet, PDF (543/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
Table 13.16 Cycles in Which Pipelined Access Can Be Used
Preceding Access
Read
CPU
Read
X
Write
X
DMAC dual
Read
X
Write
O
DMAC single Read
O
Write
O
Legend:
O: Pipelined access possible
X: Pipelined access not possible
CPU
Write
X
X
X
O
O
O
Following Access
DMAC Dual
Read Write
O
X
O
X
X
X
O
X
O
X
O
X
DMAC Single
Read Write
O
O
O
O
X
X
O
O
O
O
O
O
Rev.4.00 Oct. 10, 2008 Page 445 of 1122
REJ09B0370-0400