SH7751 Datasheet, PDF (593/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
13.3.14 Cooperation between Master and Slave
To enable system resources to be controlled in a harmonious fashion by master and slave, their
respective roles must be clearly defined. Before DRAM or synchronous DRAM is used,
initialization operations must be carried out. Responsibility must also be assigned when a standby
operation is performed to implement the power-down state.
The design of this LSI provides for all control, including initialization, refreshing, and standby
control, to be carried out by the master mode device.
If this LSI is specified as the master in a power-on reset, it will not accept bus requests from the
slave until the BREQ enable bit (BCR1.BREQEN) is set to 1.
To ensure that the slave processor does not access memory requiring initialization before use, such
as DRAM and synchronous DRAM, until initialization is completed, write 1 to the BREQ enable
bit after initialization ends.
Before setting self-refresh mode in standby mode, etc., write 0 to the BREQ enable bit to
invalidate the BREQ signal from the slave. Write 1 to the BREQ enable bit only after the master
has performed the necessary processing (refresh settings, etc.) for exiting self-refresh mode.
13.3.15 Notes on Usage
Refresh: Auto refresh operations stop when a transition is made to standby mode, hardware
standby mode, or deep-sleep mode. If the memory system requires refresh operations, set the
memory in the self-refresh state prior to making the transition to standby mode, hardware standby
mode, or deep-sleep mode.
Bus Arbitration: On transition to standby mode or deep-sleep mode, the processor in master
mode does not release bus privileges. In systems performing bus arbitration, make the transition to
standby mode or deep-sleep mode only after setting the bus privilege release enable bit
(BCR1.BREQEN) to 0 for the processor in master mode. If the bus privilege release enable bit
remains set to 1, operation cannot be guaranteed when the transition is made to standby mode or
deep-sleep mode.
Simultaneous Use of Refresh and Bus Arbitration: With the SH7751, when performing bus
arbitration using the external device and BREQ signal, the following two failures may occur.
• When a BREQ signal is input from the external device while using DMA transfer or target
transfer by the PCIC, and DRAM/synchronous DRAM is set to CAS-before-RAS refresh and
auto-refresh in master mode (MD7 = 1), bus arbitration may not be performed correctly and
this LSI may hang up.
Rev.4.00 Oct. 10, 2008 Page 495 of 1122
REJ09B0370-0400