SH7751 Datasheet, PDF (203/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Caches
• OCI: OC invalidation bit
When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit always
returns 0 when read.
• CB: Copy-back bit
Indicates the P1 area cache write mode.
0: Write-through mode
1: Copy-back mode
• WT: Write-through bit
Indicates the P0, U0, and P3 area cache write mode. When address translation is performed,
the value of the WT bit in the page management information has priority.
0: Copy-back mode
1: Write-through mode
• OCE: OC enable bit
Indicates whether or not the OC is to be used. When address translation is performed, the OC
cannot be used unless the C bit in the page management information is also 1.
0: OC not used
1: OC used
(2) Queue Address Control Register 0 (QACR0): QACR0 can be accessed by longword-size
access from H'FF000038 in the P4 area and H'1F000038 in area 7. QACR0 specifies the area onto
which store queue 0 (SQ0) is mapped when the MMU is off.
(3) Queue Address Control Register 1 (QACR1): QACR1 can be accessed by longword-size
access from H'FF00003C in the P4 area and H'1F00003C in area 7. QACR1 specifies the area onto
which store queue 1 (SQ1) is mapped when the MMU is off.
4.3 Operand Cache (OC)
4.3.1 Configuration
The operand cache in the SH7751 adopts the direct-mapping method, and consists of 512 cache
lines. Each cache line is composed of a 19-bit tag, V bit, U bit, and 32-byte data. The operand
cache in the SH7751R adopts the 2-way set-associative method, and each way consists of 512
cache lines.
Rev.4.00 Oct. 10, 2008 Page 105 of 1122
REJ09B0370-0400