SH7751 Datasheet, PDF (35/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page Revision (See Manual for Details)
15.3.3 Multiprocessor 652
Communication
Function
Figure 15.16 Example
of SCI Receive
Operation (Example with
8-Bit Data,
Multiprocessor Bit, One
Stop Bit)
Figure replaced
15.5 Usage Notes 667, 668 Description added
Handling of TEND Flag
and TE Bit
To send a break signal during serial transmission, clear the
SPB0DT bit to 0 (designating low level), then clear the TE bit to
0 (halting transmission). When the TE bit is cleared to 0, the
transmitter is initialized regardless of its current state, and the
TxD pin becomes an output port outputting the value 0.
Handling of TEND Flag and TE Bit: The TEND flag is set to 1
when the stop bit of the final data segment is transmitted. If the
TE bit is cleared immediately after confirming that the TEND
flag was set, transmission may not complete properly because
stop bit transmission processing is still underway. Therefore,
wait at least 0.5 serial clock cycles (1.5 cycles if two stop bits
are used) after confirming that the TEND flag was set before
clearing the TE bit.
17.1 Overview
719
Description amended
The serial communication interface (SCI) supports a subset of
the ISO/IEC 7816-3 (identification cards) standard as an
extended function.
17.2.3 Serial Control 724
Register (SCSCR1)
Description added
Bits 3 and 2—Reserved:
17.2.4 Serial Status 726
Register (SCSSR1)
Description added
Bits 1 and 0—Reserved:
19.1.2 Block Diagram 770
Figure amended
Figure 19.1 Block
Diagram of INTC
Interrupt
request
SR
IMASK
CPU
Rev.4.00 Oct. 10, 2008 Page xxxv of xcviii
REJ09B0370-0400