SH7751 Datasheet, PDF (159/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. Programming Model
branches to the start address of the user-coded exception service routine found from the sum of the
contents of the vector base address and the vector offset. See section 5, Exceptions, for more
information on resets, general exceptions, and interrupts.
Program Execution State: In this state the CPU executes program instructions in sequence.
Power-Down State: In the power-down state, CPU operation halts and power consumption is
reduced. The power-down state is entered by executing a SLEEP instruction. There are three
modes in the power-down state: sleep mode, deep sleep mode, and standby mode. For details, see
section 9, Power-Down Modes.
Bus-Released State: In this state the CPU has released the bus to a device that requested it.
Transitions between the states are shown in figure 2.6.
From any state when
RESET = 0
RESET = 1 and MRESET = 0
Power-on reset state
RESET = 1
RESET = 0
Manual reset state
Reset state
RESET = 1,
MRESET = 1
Exception-handling state
Interrupt
Bus request
Bus request
clearance
Bus-released state
Exception
interrupt
End of exception
transition
processing
Bus request
Bus
clearance
request
Bus request
Bus request
clearance
Program execution state
SLEEP instruction
with STBY bit
cleared
SLEEP instruction
with STBY bit set
Interrupt
Sleep mode
Standby mode
Power-down state
Figure 2.6 Processor State Transitions
Rev.4.00 Oct. 10, 2008 Page 61 of 1122
REJ09B0370-0400