SH7751 Datasheet, PDF (24/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
13.3.3 SRAM Interface 412
Figure 13.12 SRAM
Interface Wait State
Timing (Read Strobe
Negate Timing Setting)
13.3.4 DRAM Interface 425
Refresh:
• Self-Refresh
Revision (See Manual for Details)
Figure amended
TS1 T1 Tw Tw Tw Tw T2 TH1 TH2
CKIO
A25–A0
CSn
RD/WR
*
RD
D31–D0
BS
TS1: Setup wait
WCR3.AnS
(0 to 1)
Tw: Access wait
WCR2.AnW
(0 to 15)
TH1, TH2: Hold wait
WCR3.AnH
(0 to 3)
Note: * When AnRDH is set to 1
Description deleted
After the self-refresh is cleared, the refresh controller
immediately generates a refresh request. The RAS precharge
time immediately after the end of the self-refreshing can be set
by bits TRC2–TRC0 in MCR.
• Relationship between 426
Refresh Requests and
Bus Cycle Requests
Figure 13.22 DRAM
Self-Refresh Cycle
Timing
CAS-before-RAS refreshing is performed in normal operation,
in sleep mode, and in the case of a manual reset.
Figure amended
D31−D0
Rev.4.00 Oct. 10, 2008 Page xxiv of xcviii
REJ09B0370-0400