SH7751 Datasheet, PDF (198/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

3. Memory Management Unit (MMU)
2. UTLB data array 2 write
SA and TC specified in the data field are written to the UTLB entry corresponding to the entry
set in the address field.
31
24 23
Address field _{1 1 1 1 0 1 1 1 1}
14 13
87
0
E
31
Data field
432 0
SA
Legend:
TC: Timing control bit
E: Entry
TC
SA: Space attribute bits
: Reserved bits (0 write value, undefined read value)
Figure 3.18 Memory-Mapped UTLB Data Array 2
3.8 Usage Notes
1. Address Space Identifier (ASID) in Single Virtual Memory Mode
Refer to the note in 3.3.7, Address Space Identifier (ASID).
Rev.4.00 Oct. 10, 2008 Page 100 of 1122
REJ09B0370-0400