SH7751 Datasheet, PDF (678/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
14.5.4 Notes on Use of DDT Module
1. Normal data transfer mode (channel 0)
Set DTR.ID = 00 and DTR.MD = 00. If a setting of MD = 01, 10, or 11 is made, the DMAC
will halt with an address error. In this case, the error can be cleared by reading DMAOR.AE =
1, then writing AE = 0.
2. Normal data transfer mode (channel 1 to channel 3)
If a setting of DTR.ID = 01, 10, or 11 is made, DTR.MD will be ignored.
3. Handshake protocol using the data bus (valid on channel 0 only)
a. The handshake protocol using the data bus can be executed only on channel 0. (The DTR
format must be set to DTR.ID = 00, DTR.MD = 00, and DTR.SZ ≠ 101, 110. Operation is
not guaranteed if the DTR format data settings are DTR.ID = 00, DTR. MD = 00, and
DTR.SZ ≠ 101, 110.)
b. If, during execution of the handshake protocol using the data bus for channel 0, a request is
input for one of channels 1 to 3, and after that DMA transfer is executed settings of
DTR.ID = 00, DTR.MD = 00, and DTR.SZ ≠ 101, 110 are input in the handshake protocol
using the data bus, a transfer request will be asserted for channel 0.
c. If TR only is asserted by means of the handshake protocol without use of the data bus and a
DMA transfer request is input when channel 0 DMA transfer has ended and CHCR0.TE =
1, the DMAC will freeze. Before issuing a DMA transfer request, the TE flag must be
cleared by writing CHCR0.TE = 0 after reading CHCR0.TE = 1.
4. Handshake protocol without use of the data bus
a. With the handshake protocol without use of the data bus, a DMA transfer request can be
input to the DMAC again for the channel for which transfer was requested immediately
before by asserting TR only.
b. When using the handshake protocol without use of the data bus, first make the necessary
settings in the DMAC control registers.
c. When not using the handshake protocol without use of the data bus, if TR only is asserted
without outputting DTR, a request will be issued for the channel for which DMA transfer
was requested immediately before. Also, if the first DMA transfer request after a power-on
reset is input by asserting TR only, it will be ignored and the DMAC will not operate.
5. Direct data transfer mode (valid on channel 2 only)
a. If a DMA transfer request for channel 2 is input by simultaneous assertion of DBREQ and
TR during DMA transfer execution with the handshake protocol without use of the data
bus, it will be accepted if there is space in the DDT channel 2 request queue.
b. In direct data transfer mode (with DBREQ and TR asserted simultaneously), DBREQ is not
interpreted as a bus arbitration signal, and therefore the BAVL signal is never asserted.
Rev.4.00 Oct. 10, 2008 Page 580 of 1122
REJ09B0370-0400