SH7751 Datasheet, PDF (651/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
14.5 On-Demand Data Transfer Mode (DDT Mode)
14.5.1 Operation
Setting the DDT bit to 1 in DMAOR causes a transition to on-demand data transfer mode (DDT
mode). In DDT mode, it is possible to transfer to channel 0 to 3 via the data bus and DDT module,
and simultaneously issue a transfer request, using the DBREQ, BAVL, TR, TDACK, ID [1:0],
DTR.ID, and DTR.MD signals between an external device and the DMAC. Figure 14.23 shows a
block diagram of the DMAC, DDT, BSC, and an external device (with DBREQ, BAVL, TR,
TDACK, ID [1:0], DTR.ID, and DTR.MD pins).
DMAC
SAR0
DAR0
DMATCR0
CHCR0
DREQ0–3
ddtmode tdack id[1:0]
BSC
Data buffer
DDT
Data
buffer
Request
ddtmode ^controller
bavl
TR
BAVL
DBREQ
TDACK
ID[1:0]
Memory
DTR
External
device (with
DBREQ, BAVL,
TR, TDACK,
and ID [1:0])
FIFO or
memory
Figure 14.23 On-Demand Transfer Mode Block Diagram
After first making the normal DMA transfer settings for DMAC channels 0 to 3 using the CPU, a
transfer request is output from an external device using the DBREQ, BAVL, TR, TDACK,
DTR.ID [1:0], and DTR.MD [1:0] signals (handshake protocol using the data bus). A transfer
request can also be issued simply by asserting TR, without using the external bus (handshake
protocol without use of the data bus). For channel 2, after making the DMA transfer settings in the
normal way, a transfer request can be issued directly from an external device (with DBREQ,
BAVL, TR, TDACK, DTR.ID [1:0], and DTR.MD [1:0] pins) by asserting DBREQ and TR
simultaneously .
In DDT mode, there is a choice of five modes for performing DMA transfer.
Rev.4.00 Oct. 10, 2008 Page 553 of 1122
REJ09B0370-0400