SH7751 Datasheet, PDF (32/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
14.5.2 Pins in DDT 555
Mode
Figure 14.24 shows the
system configuration in
DDT mode.
Revision (See Manual for Details)
Figure amended
SH7751/SH7751R
DBREQ/DREQ0
BAVL/DRAK0
TR/DREQ1
TDACK/DACK0
ID1, ID0/DRAK1, DACK1
CKIO
D31–D0 = DTR
External device
• TR:
Data Transfer Request 556
Format (DTR)
Figure 14.25 Data
Transfer Request
Format
Data Transfer Request
Format (DTR)
557
14.5.4 Notes on Use of 580
DDT Module
7. DTR format
581
14.6.3 Register
587
Configuration
(SH7751R)
Table 14.14 Register
Configuration
A25–A0, RAS, CAS, WE, DQMn, CKE
Synchronous
DRAM
Description amended
Assertion of TR has the following different meanings.
• In normal data transfer mode (channel 0, except channel 0),
TR is asserted, and at the same time the DTR format is
output, two cycles after BAVL is asserted.
Figure amended
31 29 28 27 26 25 24 23
0
SZ
ID MD
(Reserved)
(Reserved)
Description amended, bits 31 to 29
• 000: DTR format selected
Notes amended
Note: 4. When specifying data transfer requests using a
handshake protocol for channel 0, set DTR.ID = 00, DTR.MD =
00, and DTR.SZ ≠ 101, 110 for the DTR format.
Description amended
2. Normal data transfer mode ( channel 1 to channel 3)
Note added
Note: Do not use setting values other than the above.
Notes amended
Notes: * Bit 1 of CHCR0–CHCR7 and bits 2 and 1 of
DMAOR can only be written with 0 after being read
as 1, to clear the flags.
Rev.4.00 Oct. 10, 2008 Page xxxii of xcviii
REJ09B0370-0400