SH7751 Datasheet, PDF (858/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

18. I/O Ports
Bit 2n + 1 (n = 0–15)—Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 16-
bit port A is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port
pin set to output by bit PBnIO.
Bit 2n + 1: PBnPUP
0
1
Description
Bit m (m = 0–15) of 16-bit port A is pulled up
Bit m (m = 0–15) of 16-bit port A is not pulled up
(Initial value)
Bit 2n (n = 0–15)—Port I/O Control (PBnIO): Specifies whether each bit in the 16-bit port A is
an input or an output.
Bit 2n: PBnIO
0
1
Description
Bit m (m = 0–15) of 16-bit port A is an input
Bit m (m = 0–15) of 16-bit port A is an output
(Initial value)
18.2.2 Port Data Register A (PDTRA)
Port data register A (PDTRA) is a 16-bit readable/writable register used as a data latch for each bit
in the 16-bit port A. When a bit is set as an output, the value written to the PDTRA register is
output from the external pin. When a value is read from the PDTRA register while a bit is set as an
input, the external pin value sampled on the external bus clock is read. When a bit is set as an
output, the value written to the PDTRA register is read.
PDTRA is not initialized by a power-on or manual reset, or in standby mode, and retains its
contents.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
PB15DT PB14DT PB13DT PB12DT PB11DT PB10DT
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
9
PB9DT
—
R/W
8
PB8DT
—
R/W
Bit:
Initial value:
R/W:
7
PB7DT
—
R/W
6
PB6DT
—
R/W
5
PB5DT
—
R/W
4
PB4DT
—
R/W
3
PB3DT
—
R/W
2
PB2DT
—
R/W
1
PB1DT
—
R/W
0
PB0DT
—
R/W
Rev.4.00 Oct. 10, 2008 Page 760 of 1122
REJ09B0370-0400