SH7751 Datasheet, PDF (537/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D31–D0
(read)
13. Bus State Controller (BSC)
Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Td5 Td6 Td7 Td8
H/L
H/L
c1
c5
c1 c2 c3 c4 c5 c6 c7 c8
BS
CKE
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.29 Burst Read Timing (RAS Down, Same Row Address)
Rev.4.00 Oct. 10, 2008 Page 439 of 1122
REJ09B0370-0400