SH7751 Datasheet, PDF (67/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15.2.9 Bit Rate Register (SCBRR1)................................................................................ 623
15.3 Operation........................................................................................................................... 631
15.3.1 Overview.............................................................................................................. 631
15.3.2 Operation in Asynchronous Mode ....................................................................... 633
15.3.3 Multiprocessor Communication Function............................................................ 644
15.3.4 Operation in Synchronous Mode ......................................................................... 655
15.4 SCI Interrupt Sources and DMAC .................................................................................... 665
15.5 Usage Notes ...................................................................................................................... 666
Section 16 Serial Communication Interface with FIFO (SCIF)............................. 671
16.1 Overview........................................................................................................................... 671
16.1.1 Features................................................................................................................ 671
16.1.2 Block Diagram ..................................................................................................... 673
16.1.3 Pin Configuration................................................................................................. 674
16.1.4 Register Configuration......................................................................................... 674
16.2 Register Descriptions ........................................................................................................ 675
16.2.1 Receive Shift Register (SCRSR2)........................................................................ 675
16.2.2 Receive FIFO Data Register (SCFRDR2) ........................................................... 675
16.2.3 Transmit Shift Register (SCTSR2) ...................................................................... 676
16.2.4 Transmit FIFO Data Register (SCFTDR2) .......................................................... 676
16.2.5 Serial Mode Register (SCSMR2)......................................................................... 677
16.2.6 Serial Control Register (SCSCR2)....................................................................... 679
16.2.7 Serial Status Register (SCFSR2).......................................................................... 682
16.2.8 Bit Rate Register (SCBRR2)................................................................................ 688
16.2.9 FIFO Control Register (SCFCR2) ....................................................................... 689
16.2.10 FIFO Data Count Register (SCFDR2) ................................................................. 692
16.2.11 Serial Port Register (SCSPTR2) .......................................................................... 693
16.2.12 Line Status Register (SCLSR2) ........................................................................... 700
16.3 Operation........................................................................................................................... 701
16.3.1 Overview.............................................................................................................. 701
16.3.2 Serial Operation ................................................................................................... 703
16.4 SCIF Interrupt Sources and the DMAC ............................................................................ 713
16.5 Usage Notes ...................................................................................................................... 714
Section 17 Smart Card Interface ..................................................................................... 719
17.1 Overview........................................................................................................................... 719
17.1.1 Features................................................................................................................ 719
17.1.2 Block Diagram ..................................................................................................... 720
17.1.3 Pin Configuration................................................................................................. 721
17.1.4 Register Configuration......................................................................................... 721
Rev.4.00 Oct. 10, 2008 Page lxvii of xcviii
REJ09B0370-0400