SH7751 Datasheet, PDF (632/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
(b) DDT Mode
Table 14.9 shows the memory interfaces that can be specified for the transfer source and transfer
destination in DMA transfer initiated by an external request supported by this LSI in DDT mode.
Table 14.9 External Request Transfer Sources and Destinations in DDT Mode
Transfer Direction (Settable Memory Interface)
Transfer Source
Transfer Destination
Usable
Address DMAC
Mode Channels
1 Synchronous DRAM
External device with DACK
Single 0, 1, 2, 3
2 External device with DACK
Synchronous DRAM
Single 0, 1, 2, 3
3 Synchronous DRAM
SRAM-type, MPX, PCMCIA * Dual
1, 2, 3
4 SRAM-type, MPX, PCMCIA * Synchronous DRAM
Dual
1, 2, 3
5 SRAM-type, DRAM, PCMCIA,
MPX
SRAM-type, MPX, PCMCIA * Dual
1, 2, 3
6 SRAM-type, MPX, PCMCIA
* SRAM-type, DRAM, PCMCIA,
MPX
Dual
1, 2, 3
Notes: "SRAM-type" in the table indicates an SRAM, byte control SRAM, or burst ROM setting.
The only memory interface on which single address mode transfer is possible in DDT mode
is synchronous DRAM.
When performing dual address mode transfer, make the DACK output setting for the
SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface.
* DACK output setting in dual address mode transfer
Bus Mode and Channel Priority Order
When, for example, channel 1 is transferring data in burst mode, and a transfer request is issued to
channel 0, which has a higher priority, the channel 0 transfer is started immediately.
If fixed mode has been set for the priority levels (CH0 > CH1), transfer on channel 1 is continued
after transfer on channel 0 is completely finished, whether cycle steal mode or burst mode is set
for channel 0.
If round robin mode has been set for the priority levels, transfer on channel 1 is restarted after one
transfer unit of data is transferred on channel 0, whether cycle steal mode or burst mode is set for
channel 0. Channel execution alternates in the order: channel 1 → channel 0 → channel 1 →
channel 0.
An example of round robin mode operation is shown in figure 14.11.
Rev.4.00 Oct. 10, 2008 Page 534 of 1122
REJ09B0370-0400