SH7751 Datasheet, PDF (501/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
Area 5: For area 5, external address bits 28 to 26 are 101.
SRAM, MPX, burst ROM, and a PCMCIA interface can be set to this area.
When SRAM interface is set, a bus width of 8, 16, or 32 bits can be selected with bits A5SZ1 and
A5SZ0 in the BCR2 register. When burst ROM interface is set, a bus width of 8, 16 or 32 bits can
be selected with bits A5SZ1 and A5SZ0 in BCR2. When MPX interface is set, a bus width of 32
bit should be selected with bits A5SZ1 and A5SZ0 in BCR2. When a PCMCIA interface is set,
either 8 or 16 bits should be selected with bits A5SZ1 and A5SZ0 in BCR2. For details, see
Memory Bus Width in section 13.1.5, Overview of Areas.
When area 5 is accessed with SRAM interface set, the CS5 signal is asserted. In addition, the RD
signal, which can be used as OE, and write control signals WE0 to WE3, are asserted. When a
PCMCIA interface is connected, the CE1A and CE2A signals, the RD signal, which can be used
as OE, and the WE1, WE2, WE3, and WE0 signals, which can be used as WE, ICIORD,
ICIOWR, and REG, respectively, are asserted.
As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A5W2 to A5W0
in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means
of the external wait pin (RDY).
When the burst function is used, the number of burst cycle transfer states is determined in the
range 2 to 9 according to the number of waits.
The read/write strobe signal address and CS setup and hold times can be set within a range of 0–1
and 0–3 cycles, respectively, by means of bit A5S0 and bits A5H1 and A5H0 in the WCR3
register.
When a PCMCIA interface is used, the address CE1A and CE2A setup and hold times with
respect to the read/write strobe signals can be set in the range of 0 to 15 cycles with bits AnTED1
and AnTED0, and bits AnTEH1 and AnTEH0, in the PCR register. In addition, the number of
wait cycles can be set in the range 0 to 50 with bits AnPCW1 and AnPCW0. The number of waits
set in PCR is added to the number of waits set in WCR2.
Rev.4.00 Oct. 10, 2008 Page 403 of 1122
REJ09B0370-0400