SH7751 Datasheet, PDF (709/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Serial Communication Interface (SCI)
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor
format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only
valid in asynchronous mode; it is invalid in synchronous mode.
For details of the multiprocessor communication function, see section 15.3.3, Multiprocessor
Communication Function.
Bit 2: MP
0
1
Description
Multiprocessor function disabled
Multiprocessor format selected
(Initial value)
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the on-
chip baud rate generator. The clock source can be selected from Pck, Pck/4, Pck/16, and Pck/64,
according to the setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 15.2.9, Bit Rate Register (SCBRR1).
Bit 1: CKS1 Bit 0: CKS0
0
0
1
1
0
1
Note: Pck: Peripheral clock
Description
Pck clock
Pck/4 clock
Pck/16 clock
Pck/64 clock
(Initial value)
15.2.6 Serial Control Register (SCSCR1)
Bit:
7
6
5
4
TIE
RIE
TE
RE
Initial value:
0
0
0
0
R/W: R/W
R/W
R/W
R/W
3
MPIE
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
0
CKE0
0
R/W
The SCSCR1 register performs enabling or disabling of SCI transfer operations, serial clock
output in asynchronous mode, and interrupt requests, and selection of the serial clock source.
Rev.4.00 Oct. 10, 2008 Page 611 of 1122
REJ09B0370-0400