SH7751 Datasheet, PDF (984/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
Bit 6—Bus Master Arbitration (BMABT): Controls the PCI bus arbitration mode of the PCIC
when the PCIC is operating as the host. When the PCIC is non-host, the value of this bit is
ignored.
Bit 6: BMABT
0
1
Description
Fixed priority order (device 0 (PCIC) > device 1 > device 2 > device 3 >
device 4)
(Initial value)
Pseudo round-ribbon (The priority level of the device with bus privileges is
set lowest at the next access.)
Bit 5—Mode 10 Pin Monitor (MD10): Monitors the PCIREQ3/MD10 pin value in a power-on
reset by means of the RESET pin.
Bit 5: MD10
0
1
Description
Host bridge function (arbitration) enabled
Host bridge function disabled
Bit 4—Mode 9 Pin Monitor (MD9): Monitors the PCIREQ2/MD9 pin value in a power-on reset
by means of the RESET pin.
Bit 4: MD9
0
1
Description
PCICLK used as PCI clock
Feedback input clock from CKIO used as PCI clock
Bit 3—SERR Output (SERR): Software control of SERR output. This bit is valid only when bit
8 (SER) of the PCICONFI register is “1”. When “1” is written to this bit, SERR is asserted for 1
clock. This bit always returns “0” when read. Used when the PCIC is not the host. If used when
the PCIC is the host, an SERR assert interrupt is generated to the CPU.
Bit 3: SERR
0
1
Description
SERR pin at Hi-Z (driven to High by pull-up resistor)
Assert SERR (Low output)
(Initial value)
Rev.4.00 Oct. 10, 2008 Page 886 of 1122
REJ09B0370-0400