SH7751 Datasheet, PDF (519/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

CKIO
Address
CSn
13. Bus State Controller (BSC)
Tnop Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
c1
c2
c8
RD/WR
RAS
CASn
D31–D0
(read)
D31–D0
(write)
End of RAS down mode
d1
d1
d2
d2
d8
d8
BS
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.19 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(Fast Page Mode, RCD = 0, AnW = 0)
Rev.4.00 Oct. 10, 2008 Page 421 of 1122
REJ09B0370-0400