SH7751 Datasheet, PDF (323/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Pipelining
(a) Serial execution: non-parallel-executable instructions
SHAD R0,R1
ADD R2,R3
next
1 issue cycle
I
D EX NA S
I
D EX NA S
1 stall cycle
I
D _...
(b) Parallel execution: parallel-executable and no dependency
ADD R2,R1
MOV.L @R4,R5
1 issue cycle
I
D EX NA S
I
D EX MA S
EX-group SHAD and EX-group ADD
cannot be executed in parallel. Therefore,
SHAD is issued first, and the following
ADD is recombined with the next
instruction.
EX-group ADD and LS-group MOV.L can
be executed in parallel. Overlapping of
stages in the 2nd instruction is possible.
(c) Issue rate: multi-step instruction
AND.B#1,@(R0,GBR)
MOV R1,R2
next
4 issue cycles
I
D SX MA S
D SX NA S
D SX NA S
D SX MA S
I
i
D
E
A
4 stall cycles
I ...
AND.B and MOV are fetched
simultaneously, but MOV is stalled due to
resource locking. After the lock is released,
MOV is refetched together with the next
instruction.
S
(d) Branch
BT/S L_far
ADD R0,R1
SUB R2,R3
BT/S L_far
ADD R0,R1
L_far
BT L_skip
ADD #1,R0
L_skip:
I
D EX NA S
I
D EX NA S
I
D EX NA S
No stall occurs if the branch is not taken.
2-cycle latency for I-stage of branch destination
I
D EX NA S
I
D EX NA S
1 stall cycle
I
D ...
If the branch is taken, the I-stage of the
branch destination is stalled for the period
of latency. This stall can be covered with a
delay slot instruction which is not parallel-
executable with the branch instruction.
I
D EX NA S
I
D
—— —
I
D ...
No stall
Even if the BT/BF branch is taken, the I-
stage of the branch destination is not
stalled if the displacement is zero.
Figure 8.3 Examples of Pipelined Execution
Rev.4.00 Oct. 10, 2008 Page 225 of 1122
REJ09B0370-0400