SH7751 Datasheet, PDF (174/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

3. Memory Management Unit (MMU)
Here, access to an area of the PCMCIA interface by accessing an area of P1, P2, or P4 from the
CPU is disabled. In addition, the PCMCIA interface is always accessed by the DMAC with the
values of CHCRn, SSAn, CHCRn.DsAn, CHCRn.STC and CHCRn.DTC in the DMAC. For
details, see Section 14, Direct Memory Access Controller (DMAC).
P0, P3, U0 Areas: The P0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF), P3 area, and
U0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF) allow access using the cache and
address translation using the TLB. These areas can be mapped onto any external memory space in
1-, 4-, or 64-Kbyte, or 1-Mbyte, page units. When CCR is in the cache-enabled state and the
cacheability bit (C bit) in the TLB is 1, accesses can be performed using the cache. In write
accesses to the cache, switching between the copy-back method and the write-through method is
indicated by the TLB write-through bit (WT bit), and is specified in page units.
Only when the P0, P3, and U0 areas are mapped onto external memory space by means of the
TLB, addresses H'1C00 0000 to H'1FFF FFFF of area 7 in external memory space are allocated to
the control register area. This enables control registers to be accessed from the U0 area in user
mode. In this case, the C bit for the corresponding page must be cleared to 0.
P1, P2, P4 Areas: Address translation using the TLB cannot be performed for the P1, P2, or P4
area (except for the store queue area). Accesses to these areas are the same as for physical address
space. The store queue area can be mapped onto any external memory space by the MMU.
However, operation in the case of an exception differs from that for normal P0, U0, and P3 spaces.
For details, see section 4.7, Store Queues.
3.3.4 On-Chip RAM Space
In the SH-4, half of the operand cache can be used as on-chip RAM. This can be done by changing
the CCR settings.
When the operand cache is used as on-chip RAM (CCR.ORA = 1), P0, U0 area addresses H'7C00
0000 to H'7FFF FFFF are an on-chip RAM area. Data accesses (byte/word/longword/quadword)
can be used in this area. This area can only be used in RAM mode.
3.3.5 Address Translation
When the MMU is used, the virtual address space is divided into units called pages, and
translation to physical addresses is carried out in these page units. The address translation table in
external memory contains the physical addresses corresponding to virtual addresses and additional
information such as memory protection codes. Fast address translation is achieved by caching the
contents of the address translation table located in external memory into the TLB. In the SH-4,
basically, the ITLB is used for instruction accesses and the UTLB for data accesses. In the event
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