SH7751 Datasheet, PDF (93/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment .......................... 394
Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment .......................... 395
Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment ............................ 396
Table 13.11 32-Bit External Device/Little-Endian Access and Data Alignment ....................... 397
Table 13.12 16-Bit External Device/Little-Endian Access and Data Alignment ....................... 398
Table 13.13 8-Bit External Device/Little-Endian Access and Data Alignment ......................... 399
Table 13.14 Relationship between AMXEXT and AMX2–0 Bits and Address Multiplexing... 414
Table 13.15 Example of Correspondence between this LSI and Synchronous
DRAM Address Pins (32-Bit Bus Width, AMX2–AMX0 = 000, AMXEXT = 0) 429
Table 13.16 Cycles in Which Pipelined Access Can Be Used ................................................... 445
Table 13.17 Relationship between Address and CE When Using PCMCIA Interface .............. 462
Section 14 Direct Memory Access Controller (DMAC)
Table 14.1 DMAC Pins ............................................................................................................ 501
Table 14.2 DMAC Pins in DDT Mode .................................................................................... 502
Table 14.3 DMAC Registers .................................................................................................... 502
Table 14.4 Selecting External Request Mode with RS Bits ..................................................... 521
Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits ...................... 522
Table 14.6 Supported DMA Transfers ..................................................................................... 526
Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode ......... 532
Table 14.8 External Request Transfer Sources and Destinations in Normal DMA Mode ....... 533
Table 14.9 External Request Transfer Sources and Destinations in DDT Mode ..................... 534
Table 14.10 Conditions for Transfer between External Memory and an External Device
with DACK, and Corresponding Register Settings ................................................ 552
Table 14.11 Usable SZ, ID, and MD Combination in DDT Mode............................................. 557
Table 14.12 DMAC Pins ............................................................................................................ 584
Table 14.13 DMAC Pins in DDT Mode .................................................................................... 585
Table 14.14 Register Configuration ........................................................................................... 586
Table 14.15 Channel Selection by DTR Format (DMAOR.DBL = 1)....................................... 594
Table 14.16 Notification of Transfer Channel in Eight-Channel DDT Mode ............................ 596
Table 14.17 Function of BAVL.................................................................................................. 596
Table 14.18 DTR Format for Clearing Request Queues ............................................................ 597
Table 14.19 DMAC Interrupt-Request Codes............................................................................ 598
Section 15 Serial Communication Interface (SCI)
Table 15.1 SCI Pins.................................................................................................................. 606
Table 15.2 SCI Registers.......................................................................................................... 606
Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode.................. 625
Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode.................... 628
Rev.4.00 Oct. 10, 2008 Page xciii of xcviii
REJ09B0370-0400