SH7751 Datasheet, PDF (798/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Serial Communication Interface with FIFO (SCIF)
16.2.12 Line Status Register (SCLSR2)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
ORER
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
(R/W)*
Note: * Only 0 can be written, to clear the flag.
Bits 15 to 1—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 0—Overrun Error (ORER): Indicates that an overrun error occurred during reception,
causing abnormal termination.
Bit 0: ORER
0
Description
Reception in progress, or reception has ended normally*¹
[Clearing conditions]
• Power-on reset or manual reset
• When 0 is written to ORER after reading ORER = 1
(Initial value)
1
An overrun error occurred during reception*²
[Setting condition]
When the next serial reception is completed while the receive FIFO is full
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in
SCSCR2 is cleared to 0.
2. The receive data prior to the overrun error is retained in SCFRDR2, and the data
received subsequently is lost. Serial reception cannot be continued while the ORER flag
is set to 1.
Rev.4.00 Oct. 10, 2008 Page 700 of 1122
REJ09B0370-0400