SH7751 Datasheet, PDF (18/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
9.9.1 In Reset
255
Figure 9.2 STATUS
Output in Manual Reset
Revision (See Manual for Details)
Figure amended
CKIO
RESET (High)
MRESET*
Must be asserted for
t_RESW or longer
9.9.5 Hardware
264
Standby Mode Timing
Figure 9.15 Timing
When VDD-RTC Power
is Off → On
STATUS Normal
Figure amended
≥ 0 Bcyc
Reset
0–30 Bcyc
V_DD-RTC
CA
Power-on oscillation
settling time
Normal
V_DD, V_DDQ^*
RESET
Min 0s
9.10 Usage Notes
10.1.1 Features
Note: * V_DD, V_DD-PLL1/2, V_DDQ, V_DD-CPG
264, 265 Newly added
267
Description amended
• Three clocks
The CPG can generate the CPU clock (Ick) used by the
CPU, FPU, caches, and TLB, the peripheral module clock
(Pck) used by the peripheral modules, and the bus clock
(Bck) used by the external bus interface.
…
• Frequency change function
PLL (phase-locked loop) circuits and a frequency divider in
the CPG enable the CPU clock, bus clock, and peripheral
module clock frequencies to be changed . Frequency
changes are performed by software in accordance with the
settings in the frequency control register (FRQCR).
Rev.4.00 Oct. 10, 2008 Page xviii of xcviii
REJ09B0370-0400