SH7751 Datasheet, PDF (100/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

1. Overview
Table 1.1 SH7751/SH7751R Group Features
Item
LSI
Features
• Superscalar architecture: Parallel execution of two instructions
• External buses (SH buses)
⎯ Separate 26-bit address and 32-bit data buses
⎯ External bus frequency of 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus
frequency
• External bus (PCI bus):
⎯ 32-bit address/data multiplexing
⎯ Selection of internal clock or external PCI-dedicated clock
CPU
• Renesas Technology original SuperH architecture
• 32-bit internal data bus
• General register file:
⎯ Sixteen 32-bit general registers (and eight 32-bit shadow registers)
⎯ Seven 32-bit control registers
⎯ Four 32-bit system registers
• RISC-type instruction set (upward-compatible with SuperH Series)
⎯ Fixed 16-bit instruction length for improved code efficiency
⎯ Load-store architecture
⎯ Delayed branch instructions
⎯ Conditional execution
⎯ C-based instruction set
• Superscalar architecture (providing simultaneous execution of two
instructions) including FPU
• Instruction execution time: Maximum 2 instructions/cycle
• Virtual address space: 4 Gbytes (448-Mbyte external memory space)
• Space identifier ASIDs: 8 bits, 256 virtual address spaces
• On-chip multiplier
• Five-stage pipeline
Rev.4.00 Oct. 10, 2008 Page 2 of 1122
REJ09B0370-0400