SH7751 Datasheet, PDF (589/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
occur simultaneously, priority is given, in high-to-low order, to a bus request from an external
device, a refresh request, the DMAC, and the CPU. See section 13.3.15, Notes on Usage.
To prevent incorrect operation of connected devices when the bus is transferred between master
and slave, all bus control signals are negated before the bus is released. When mastership of the
bus is received, also, bus control signals begin driving the bus from the negated state. Since
signals are driven to the same value by the master and slave exchanging the bus, output buffer
collisions can be avoided.
Bus transfer is executed between bus cycles.
When the bus release request signal (BREQ) is asserted, this LSI releases the bus as soon as the
currently executing bus cycle ends, and outputs the bus use permission signal (BACK). However,
bus release is not performed during multiple bus cycles generated because the data bus width is
smaller than the access size (for example, when performing longword access to 8-bit bus width
memory) or during a 32-byte transfer such as a cache fill or write-back. In addition, bus release is
not performed between read and write cycles during execution of a TAS instruction, or between
read and write cycles when DMAC dual address transfer is executed. When BREQ is negated,
BACK is negated and use of the bus is resumed. See appendix D, Pin Functions, for the pin states
when the bus is released.
When a refresh request is generated, this LSI performs a refresh operation as soon as the currently
executing bus cycle ends. However, refresh operations are deferred during multiple bus cycles
generated because the data bus width is smaller than the access size (for example, when
performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as a
cache fill or write-back, and also between read and write cycles during execution of a TAS
instruction, and between read and write cycles when DMAC dual address transfer is executed.
Refresh operations are also deferred in the bus-released state.
If the synchronous DRAM interface is set to the RAS down mode the PALL command is issued
before a refresh cycle occurs or before the bus is released by bus arbitration.
As the CPU in this LSI is connected to cache memory by a dedicated internal bus, reading from
cache memory can still be carried out when the bus is being used by another bus master inside or
outside this LSI. When writing from the CPU, an external write cycle is generated when write-
through has been set for the cache in this LSI, or when an access is made to a cache-off area.
There is consequently a delay until the bus is returned.
When this LSI wants to take back the bus in response to an internal memory refresh request, it
negates BACK. On receiving the BACK negation, the device that asserted the external bus release
request negates BREQ to release the bus. The bus is thereby returned to this LSI, which then
carries out the necessary processing.
Rev.4.00 Oct. 10, 2008 Page 491 of 1122
REJ09B0370-0400