SH7751 Datasheet, PDF (478/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
Bits 12 to 10—CAS-Before-RAS Refresh RAS Assertion Period (TRAS2–TRAS0): When the
DRAM interface is set, these bits set the RAS assertion period in CAS-before-RAS refreshing.
When the synchronous DRAM interface is set, the bank active command is not issued for a period
set by TPC[2:0] and TRAS[2:0] bits after an auto-refresh command is issued.
Note: For setting values and the period during which no command is issued, see 23.3.3, Bus
Timing.
Command Interval after
RAS/DRAM
Synchronous DRAM
Bit 12: TRAS2 Bit 11: TRAS1 Bit 10: TRAS0 Assertion Time Refresh
0
0
0
2
4 + TRC (Initial value)
1
3
5 + TRC
1
0
4
6 + TRC
1
5
7 + TRC
1
0
0
6
8 + TRC
1
7
9 + TRC
1
0
8
10 + TRC
1
9
11 + TRC
Note: TRC (Bits 29 to 27): RAS precharge interval at end of refresh
Bit 9—Burst Enable (BE): Specifies whether burst access is performed on DRAM interface. In
synchronous DRAM access, burst access is always performed regardless of the specification of
this bit. The DRAM transfer mode depends on EDOMODE.
BE
EDOMODE
8/16/32/64-Bit Transfer
32-Byte Transfer
0
0
Single
Single
1
Setting prohibited
Setting prohibited
1
0
Single/fast page*
Fast page
1
EDO
EDO
Note: * In fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit
bus
Rev.4.00 Oct. 10, 2008 Page 380 of 1122
REJ09B0370-0400