SH7751 Datasheet, PDF (475/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
Bit 31—RAS Down (RASD): Sets RAS down mode. When RAS down mode is used, set BE to 1.
Do not set RAS down mode in slave mode or when areas 2 and 3 are both designated as
synchronous DRAM interface.
Bit 31: RASD
Description
0
Auto-precharge mode
(Initial value)
1
RAS down mode
Note: When synchronous DRAM is used in RAS down mode, set bits DMAIW2–DMAIW0 to 000
and bits A3IW2–A3IW0 to 000.
Bit 30—Mode Register Set (MRSET): Set when a synchronous DRAM mode register setting is
used. See Power-On Sequence in section 13.3.5, Synchronous DRAM Interface.
Bit 30: MRSET
0
1
Description
All-bank precharge
Mode register setting
(Initial value)
Bits 26 to 24, 22, and 18—Reserved: These bits should only be written with 0.
Bits 29 to 27—RAS Precharge Time at End of Refresh (TRC2–TRC0)
(Synchronous DRAM: auto- and self-refresh both enabled, DRAM: auto- and self-refresh both
enabled)
Note: For setting values and the period during which no command is issued, see 23.3.3, Bus
Timing.
Bit 29: TRC2
0
1
Bit 28: TRC1
0
1
0
1
Bit 27: TRC0
0
1
0
1
0
1
0
1
RAS Precharge Time
Immediately after Refresh
0
(Initial value)
3
6
9
12
15
18
21
Rev.4.00 Oct. 10, 2008 Page 377 of 1122
REJ09B0370-0400