SH7751 Datasheet, PDF (531/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D31–D0
(read)
Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Tpc
Row
Row
H/L
Row
c1
c1
BS
CKE
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.25 Basic Timing for Synchronous DRAM Single Read
Burst Write: The timing chart for a burst write is shown in figure 13.26. In this LSI, a burst write
occurs only in the event of 32-byte transfer. In a burst write operation, the WRIT command is
issued in the Tc1 cycle following the Tr cycle in which the ACTV command is output and, 4
cycles later, the WRITA command is issued. In the write cycle, the write data is output at the same
time as the write command. In the case of the write with auto-precharge command, precharging of
the relevant bank is performed in the synchronous DRAM after completion of the write command,
and therefore no command can be issued for the same bank until precharging is completed.
Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is
also added as a wait interval until precharging is started following the write command. Issuance of
a new command for the synchronous DRAM is postponed during this interval. The number of
Trwl cycles can be specified by bits TRWL2–TRWL0 in MCR. Access starts from 16-byte
Rev.4.00 Oct. 10, 2008 Page 433 of 1122
REJ09B0370-0400