SH7751 Datasheet, PDF (1061/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
22.4.4 Endian Control in Target Transfers (Memory Read/Memory Write)
In target transfers, for memory read and memory write that perform data transfer between the local
bus and the PCI bus, big/little endian conversion is required in the same way as for DMA transfers
when the local bus is set for big endians. Word/longword boundary modes are not supported in the
case of target transfers. As shown in table 22.12, the byte data boundary mode is used, for all
transfers.
The access sizes supported in the case of target transfers are as follows: For target reads (local bus
to PCI bus), longword only. For target writes (PCI bus to local bus), longword/word/byte. In target
write operations, the byte, word and longword data in the PCIC are transferred to the local bus in
one or two transfer operations depending on the type of the byte enable signal of the PCI bus.
For example, when C/BE = B'1010, byte access to the local bus is generated twice. When C/BE =
B'1000, byte access and word access are each generated once.
Table 22.12 Target Transfer Access Size and Endian Conversion Mode
Local Bus
Endian
Big endian
Little endian
Data Transfer
Direction
Target read
Target write
Target read
Target write
Access
Size
LW
B, W, LW
LW
B, W, LW
Endian Conversion Mode
W/LW Boundary
Mode (1 to 3)
Byte Data Boundary
Mode
No
Yes
No
Yes
Conversion not
required
Conversion not
required
Rev.4.00 Oct. 10, 2008 Page 963 of 1122
REJ09B0370-0400